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日期:2024-09-01
Fermi-level pinning of poly-Si and metal-silicide gate materials on Hf-based gate dielectrics has been ......
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日期:2024-09-05
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 51, NO. 6, JUNE 2004. 971. Fermi-Level ......
Interfaces of high-k dielectrics on GaAs: Their common features and the relationship with Fermi leve
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日期:2024-09-04
We have studied Fermi level pinning (FLP) of Hf-based high-k gate stacks based on thermodynamics based on an O vacancy model. Our study shows that FLP cannot be avoided when the system is under thermal equilibrium. O exposure to aim O vacancy ......
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日期:2024-09-01
Fermi level pinning and mobility degradation. 12. Conclusions. New Materials for
the Gate Stack of MOS-Transistors. 2 ......
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日期:2024-09-02
High threshold voltage because of Fermi level pinning at poly-Si/High-K interface
; Degraded channel carrier mobility....
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日期:2024-08-30
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日期:2024-09-04
We report here for the first time that Fermi pinning at the polySi/metal oxide interface causes high threshold voltages in MOSFET devices. Results indicate that pinning occurs due to the interfacial Si-Hf and Si-O-Al bonds for HfO/sub 2/ and Al/sub 2/O/su...
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日期:2024-09-04
Journal of the Korean Physical Society, Vol. 55, No. 6, December 2009, pp. 2501∼2504 Fermi-Level Pinning at the Poly-Si/HfO 2 Interface Ranju Jung∗ Department of Electrophysics, Kwangwoon University, Seoul 139-701 The high threshold voltage in metal-oxide...