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Gate Stacks With High-k Dielectrics and Metal Electrodes: Fermi Level Pinning and Dipoles Induced by
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日期:2024-07-13
Manhong Zhang, Ph.D.: studied high-k gate dielectrics and metal gate electrodes at University of Texas at Austin, Texas, United States. Professor at Institute of Microelectronics, Chinese Academy of Sciences, Beijing, China. Current research is high-k die...
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日期:2024-07-10
Fermi-level pinning of poly-Si and metal-silicide gate materials on Hf-based gate
dielectrics has been systematically ......
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日期:2024-07-08
9 Jan 2008 ... Too large high-k cause significant short channel effect ..... Flat-band shift due to
Fermi Level Pinning....
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日期:2024-07-14
Fermi level pinning and mobility degradation. 12. Conclusions. New Materials for
the Gate Stack of MOS-Transistors. 2 ......
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日期:2024-07-14
Leading material for high performance applications (k=20-25) ... ϕ. CNL. Effective
workfunction & Fermi level pinning ......
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日期:2024-07-14
high- dielectrics differ appreciably from their values on SiO2 or in a vacuum. We
also .... illustrates the case where the metal Fermi level is above ... 2(a) illustrates
the varying degrees of pinning of metal ......
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日期:2024-07-11
High threshold voltage because of Fermi level pinning at poly-Si/High-K interface
; Degraded channel carrier mobility....
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日期:2024-07-14
ABSTRACT Fermi-level pinning of poly-Si and metal-silicide gate materials on Hf
-based gate dielectrics has been ......