Minimizing Clock Domain Crossing in Network on Chip Interconnect

Minimizing Clock Domain Crossing in Network on Chip Interconnect

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日期:2024-07-29
Minimizing Clock Domain Crossing in Network on Chip Interconnect Parag Kulkarni1, Puneet Gupta2, Rudy Beraha3 1Synopsys, 1101 Slater Road, Durham, NC USA 2Department of Electrical Engineering, University of California, Los Angeles 3Qualcomm, 5775 ......看更多